Synthesizable Bfms

Synthesizable BFMs

EasyIC provides fully synthesizable Bus Functional Models (sBFMs) that can be used for ASIC/SoC validation and SoC prototyping on FPGA platforms. The synthesizable models enables users to extensively debug their device in simulation and then conduct intensive validation in their emulation environment or on FPGA.

The models are delivered as fully Verilog RTL synthesizable code together with a synthesizable sanity testbench to confirm correct instantiation. The complete verification environment for each BFM, coded in SystemVerilog and using the UVM methodology, is also available on request.

LPDDR5 BFM

The EasyIC synthesizable LPDDR5 BFM is a fully functional, configurable, and cycle-accurate model based on the JESD209-5A JEDEC standard. The model offers debugging capabilities via a APB based backdoor interface for system validation.

DDR5 BFM

The EasyIC synthesizable DDR5 BFM is a fully functional, configurable, and cycle-accurate model based on the JESD79-5 JEDEC standard. The model offers debugging capabilities via a APB based backdoor interface for system validation. 

LPDDR4 BFM

The EasyIC synthesizable LPDDR4 BFM is a fully functional, configurable, and cycle-accurate model based on the JESD209-4 JEDEC standard. The model offers debugging capabilities via a APB based backdoor interface for system validation.

 

DDR4 BFM

The EasyIC synthesizable DDR4 model is a fully functional, configurable, and cycle-accurate model based on the JESD79-4 JEDEC standard. The model offers debugging capabilities via a APB based backdoor interface for system validation.

DDR4 BFM

LPDDR3 BFM

The EasyIC synthesizable LPDDR3 model is a fully functional, configurable, and cycle-accurate model based on the JESD209-3B JEDEC. The model offers debugging capabilities via a APB based backdoor interface for system validation.

DDR3 BFM

The EasyIC synthesizable DDR3 model is a fully functional, configurable, and cycle-accurate model based on the JESD79-3F JEDEC standard. The model offers debugging capabilities via a APB based backdoor interface for system validation.

DDR BFM TO MIG BRIDGE

The EasyIC SDRAM to Xilinx MIG Bridge is a synthesizable module which facilitates the memory expansion of any of the EasyIC synthesizable DDR BFM models. The Bridge is able to accommodate up to four DDR BFMs ports in parallel while sharing the same physical DDR memory mapped into a Xilinx MIG module. It enables unlimited memory size together with all the features of the EasyIC BFMs.

DDR BFM TO MIG BRIDGE

I3C BFM

The EasyIC synthesizable I3C model is a configurable, fully functional model compliant to the MIPI I3C specification (i.e. I3C Master, I3C Slave, I2C Slave). It includes a backdoor APB interface for control, monitoring and data exchange (with the internal FIFO). It also includes error detection and controlled error injection on SDR and HDR modes.

I3C BFM
Product Briefs of the BFMs
are available from the
Design&Reuse IP portal.

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