How EasyIC’s internally developed co-verifier tool addresses this challenge
Innovation in application areas such as Machine Learning, Artificial Intelligence, 5G/6G and Smart Driving is demanding ever-increasing complex products made up of layers of hardware and software. At the heart of many of these products is a System-on-Chip, itself made up of multiple hardware elements and accompanying software layers.
The breadth and depth of Arm technology available today enables innovative companies to easily define the most optimum Arm based CPU System-on-Chip for their target applications. As an Arm Approved Design Partner, EasyIC collaborates with such companies to build and verify their Arm based System-on-Chips.
To verify one of these complex CPU systems, we have found that the verification team assembled must have a wide range of skills and expertise spanning both the hardware and software domains. The team must be able to verify the system connectivity, data flow and the system performance. In addition, the team must also develop and deliver the system bare-metal software that can be used as the foundation for applications created by the customer software development team.
Our system verification teams therefore includes both hardware verification engineers and embedded software engineers. Normally, the hardware verification engineer of today is comfortable developing SystemVerilog testcases in their UVM environment. Likewise, the embedded software engineer is comfortable developing firmware and drivers in their relevant software development environment for the target CPU.
In CPU system co-verification, these worlds come together and the hardware engineer and software engineer must operate across these two worlds. They both must be able to use SystemVerilog/UVM testbenches and C Firmware testbenches concurrently without the need of translating code from one language to another. The challenge is therefore how to bridge the gap between the two worlds and ensure the most proficient use of the skills of the hardware engineer and software engineer.
The EasyIC Co-Verifier tool bridges the gap between hardware and software in Arm System Verification
EasyIC has developed an internal co-verification tool that successfully addresses this challenge for our mixed-discipline verification teams. The tool is used by both the hardware and software engineers on our teams to substantially reduce the cost and time of Arm system verification achieving faster Time-to-Market for our customers.
The tool enables the unified control of the UVM and Firmware testbenches from a single C or SystemVerilog testcase i.e. both testbenches can be singularly controlled from either the hardware or software world. The tool utilises a proprietary communication protocol which allows the efficient exchange of large amounts of data between the SystemVerilog and C based testbenches. The tool automatically generates the files and co-verification libraries to enable the unified testbench control from the single C or SystemVerilog testcase. The hardware verification engineer can therefore seamlessly use pre-existing software routines, while the embedded software engineer can call SystemVerilog sequences for peripherals directly from their C code.
The tool can also achieve significant acceleration of system simulations by replacing the Arm CPU with a standard protocol UVM agent. In certain scenarios, we have seen up to 30% to 40% saving in simulation time.
For future development, the tool will also provide a pathway from simulation to emulation offering the flexibility of using a mixed VIP/BFM environment. This will enable early software development and debug by the customer application software team.